The present invention relates to testing memory of a computing device, and more specifically to testing a Central Processing Unit (CPU), a system memory, and a combination thereof.
The system memory is a place where a computer, or computing device, holds current computer programs (i.e., software) as well as data that are used in executing the computer programs. A system memory is an important part of the main processing subsystem of a computing device, such as a PC, and is tied in with the processor, cache, motherboard and chipset. Since reliability of system memory is a critical factor to the availability of a computing device, it is vital to identify defective system memory, especially when the memory is connected to a CPU.
A computing device having one or more CPUs is generally coupled to write data to and read data from one or more memory devices, wherein a CPU executes code typically from a system memory and then stores results for later action. The CPU provides controls signals, such as READ and Write, to govern the way in which data is exchanged while the CPU is processing. Additionally, an address bus connects the CPU to the memory and allows the CPU to address specific memory locations for storing computational results, or for fetching program instructions to be executed by a central processor. Furthermore, a data bus provides an interconnection between the CPU and memory for transporting data to and from the CPU. One or more CPUs coupled to one or more memory devices are hereinafter referred to as a “CPU-memory system.”
Conventional system memory techniques for testing a memory coupled to a CPU write data into memory and then read it back to verify whether the actual data read from the memory is the same as the expected written data. The purpose of this test is to confirm that every storage location in a memory device is operating properly. For example if the number A5 hex is written into a particular address, that value should be stored there unit another number is written. Some memory test techniques combine several test numbers into a sequence of numbers, also known as a test pattern. Such patterns used for testing a memory's functionality include, for example, “walking ones,” “checkerboard,” etc.
With this traditional approach, three aspects of the memory are inherently tested. Those aspects include: (1) the data bus, (2) the address bus, and (3) the memory locations themselves. Traditional testing of a CPU-memory system generally detects electrical connection or logic problems between the CPU and memory, while testing the memory locations (i.e., third aspect) reveals potential catastrophic failures (e.g., inoperative memory locations). Traditional testing of the CPU-memory system also uncovers problems related to the control bus interconnections, it any.
There is a significant drawback, however, of using the traditional techniques to test the combined functionality of CPU-memory systems. In a CPU-memory system, CPUs typically handle fetching of computing instructions, also known as op-codes or “codes,” and data from the memory differently. As illustrated in FIG. 1, internal to an exemplary CPU, data is accessed from memory 114 via internal system bus 112. Bus/memory interface 110 introduces a mixture of code and data into the CPU core 104 of the CPU 102, when accessed from memory 114. Bus/memory interface 110 separates the code and data and provides them respectively to a code cache 106 and data cache 108. Code cache 106 provides instructions to the CPU core 104 (i.e., “execution unit”) for processing data, where code is conveyed by way of a code access path 105. Data cache 108 provides the data to the core 104 for processing, where data is conveyed by way of a data access path 107. Bus/memory interface 110 also recombines the code and data and sends them back out onto internal bus 112 to, for example, allow the data to be written into memory 114.
Although the data portion of an instruction and the corresponding data access path used during a data fetch operation are tested by the conventional approach, this approach fails to verify whether the memory or CPU is properly operable to in regards to the code access path. A defect in the instruction access path (i.e., code access path) between the CPU core 104 and the bus/memory interface 110 will result in illegal operation of the CPU-memory system. Furthermore, conventional testing techniques fail to detect the corruption of a code segment of a fetched instruction, which is recognized by the CPU-memory system as an invalid op code. A defective system memory, for example, may manifest in the corruption of code being accessed by the CPU during the execution of a unique sequence of instructions.
Since conventional testing techniques fail to optimally screen for defects, manufacturers, service providers and consumers both must expand significant resources to address such defects. Thus, there is a need for a system and a method for screening system memories, as well as CPU-memory systems, to detect specific failure modes that otherwise are not detected by conventionally known testing systems and methods.